Many techniques are used to increase the storage density of dynamic random access memory (DRAM). These include reducing physical cell size and the use of complex three. dimensional cell capacitors structures. These techniques are becoming increasingly more expensive. One additional dimension that has yet to be successfully exploited in commercial RAM is to store more than one bit per cell. In a DRAM cell, this technique involves storing and then subsequently sensing two or more distinct voltage levels on a cell capacitor, and is referred to as a multilevel DRAM (MLDRAM).
Referring to FIGS. 1(a) and 1(b), an illustrative example is given of how four logic pairs of two bits, 00, 01, 10, and 11 may be represented as four equally spaced voltage levels in the range VSS=0 to Vdd, that is VSS, ⅓ Vdd, ⅔ Vdd, and Vdd. In order to extract the two bits from a cell, the cell voltage must be compared to at least two of the reference levels. The most significant bit (MSB) can be determine by comparing the cell voltage with the MSB reference of Vdd/2. If the cell voltage is greater than Vdd/2, the result of the comparison yields a logical one. A second comparison is then made to determine the least significant bit (LSB). The second comparison is made with a reference level of 5Vdd/6. The result of this comparison will yield a logical one if the cell voltage is greater than 5Vdd/6, and will yield a logical zero otherwise.
If the result of the MSB comparison was a logical 0 (that is the cell voltage is less than xc2xd Vdd/2) then the second comparison is made with a LSB reference level of Vdd/6. This comparison will yield a logical 1 if the cell voltage is greater than Vdd/6 and a logical 0 otherwise.
Several different MLDRAM schemes have been proposed thusfar. These schemes differ in the techniques to store analog cell voltages as well as the techniques used to sense and restore the cell signals. The sensing and restoring techniques for conventional two level DRAMs are well known and do not vary much between designs. However, for implementing MLDRAM, the sense and restore scheme is a difficult circuit to design. The multilevel sense and restore scheme must provide the capability to extract data encoded as one of many allowed voltage ranges on a capacitor, which is referred to as the sense operation. The scheme must also provide the capability to take multiple bits of input and convert them to one of many nominal voltage levels, which is referred to as the restore operation.
There are several important parameters that should be taken into account when assessing the quality of various sensing schemes. The size of the circuitry is important in that is must at least fit in the width of one or two columns of memory cells. Further, it is desirable that the sensing scheme is insensitive to process variation. In charge sharing operations used in MLDRAM, the capacitances involved depend on many process parameters, each of which has a different impact on the cell and bit line capacitance. Further, it is preferable that the sensing scheme is insensitive to noise. DRAMs are electrically balanced so that the common mode noise rejection in the sense amplifiers is very high. This requirement is even more important for MLDRAM, since the noise margins are considerably decreased as compared with DRAMs. Finally, it is preferable that the speed of the sensing scheme is comparable to that of the speed for a DRAM.
One multilevel sense and restore method is proposed by T. Furuyama et al. (xe2x80x9cFuruyamaxe2x80x9d) in an article titled xe2x80x9cAn Experimental Two Bit/Cell Storage DRAM for Macro Cell or Memory on Logic Applicationxe2x80x9d, IEEE J. Solid State Circuits, volume 24, number 2, pages 388 to 393, April 1989 and incorporated herein by reference. In this scheme, four voltage levels are mapped to two bits, as shown in FIG. 1(b). In order to read multilevel data, a cell charge is shared with a bit line. The bit line itself is modified such that it can be split into three equal parts called sub-bit lines, as shown in FIGS. 2(a), (b) and (c). Once the cell signal charge has been shared equally across the sub-bit lines, they are isolated from one another via switches controlled by signal SWT, and a sense amplifier SA is connected to each sub bit line via a switch controlled by signal CNCT. The multilevel data is compared in parallel to three reference voltages, as shown in FIG. 1(b), diluted by the ratio of the cell capacitance to the bit-line capacitance. A data bus carries the three sense amplifier outputs to a buffer, after which the three logic values are converted into two bits according to the function shown below in Table 1. For Table 1, the sense amplifiers compare the cell charge with ⅚ Vdd, xc2xd Vdd, and ⅙ Vdd respectively.
Restoring the data involves simply disconnecting the sense amplifiers SA from the three sub-bitlines and then reconnecting the sub-bitlines together. Charge sharing will give a final voltage on the bit lines equal to an appropriate value (Vdd, 2Vdd/3, Vdd/3, or Vss). A word line is asserted, thus capturing the desired multilevel voltage in an addressed cell.
The advantages of the present scheme are that it is fast and relatively simple. Using three sense amplifiers results in two bits being available at the same time. However, this scheme also results in more area being devoted to supporting circuitry rather than to storage cells, reducing the potential density gain that MLDRAM offers. A further disadvantage of this particular scheme is its susceptibility to sensing errors from improper reference values. The potential for such errors arises from the use of global reference voltages which need to be generated on a chip and distributed across the array of sub-bit lines. Even a slight inaccuracy in the global reference voltage levels is sufficient to introduce errors into the present scheme.
Another MLDRAM scheme is proposed by P. Gillingham in a paper title xe2x80x9cA Sense and Restore Technique for Multilevel DRAMxe2x80x9d, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, volume 43, number 7, July 19969xe2x80x9d (xe2x80x9cGillinghamxe2x80x9d). The proposed scheme uses the same restore technique as the Furuyama scheme, but uses a different sensing method. The architecture of cell columns implemented uses two pairs of sub-bitlines, with each pair having a sense amplifier SAL, SAR as illustrated in FIGS. 3(a) and 3(c). The four sub-bitlines can be connected in six different ways using a transistor switch matrix as shown in FIG. 3(b). Also, each sense amplifier SAL, SAR can be disconnected from its respective sub-bitline pair through yet another set of switches controlled by signal CNCTL and CNCTR. Unlike the parallel operation of the sense amplifier used in the Furuyama scheme, the Gillingham scheme uses sequential sensing.
In sequential sensing, the result of the first sense amplifiers sensing operation is used to generate the reference voltage for the second sensing operation. An initial sensing operation compares the multi-level data to VDD /2 and the reference for the final sensing operation is generated. If the first sensing operation reveals that the cell voltage is above VDD /2 then the second sensing operation will compare (after dilution) the cell voltage to an LSB reference of 5VDD /6. Conversely, if the first sensing operation reveals that the cell voltage is below VDD /2 then VDD/6 is chosen as the LSB reference. The results of the two sensing operations produce the MSB and LSB values for the one addressed cell. At this point the data is latched at the sense amplifiers and ready for reading.
The advantage of this circuit is that it uses local components for sensing and storing operations. Therefore, the reference signal is created using the cell which is being read rather than a special reference cell as in the Furuyama scheme, thereby removing the potential for errors arising from the use of global reference voltages. However, there is a significant time penalty incurred for sequential sensing. There are also further operations that require charging of the bitlines between sensing and restoring that adds to the cycle time. A further drawback of the present system is the complexity of the control logic required. Furthermore, the present sensing scheme may also not fit easily into the bitline pitch of a DRAM process since it requires the sense amplifiers to fit into the pitch of one cell column.
A third scheme is described by T. Okuda et al. is described in a paper titled xe2x80x9cA Four Level Storage forxe2x80x94Gb DRAM,xe2x80x9d IEEE J. Solid State Circuits, Volume 32, No. 11 pages 1743 to 1747, November 1997. As in the Gillingham implementation, the reference levels are developed using sequential sensing. However, rather than using local charge sharing to generate the LSB reference voltages, a capacitive coupling method is used. The value of the most significant bit is placed onto a capacitor which bumps a second reference value up or down from the middle reference to one or the two possible LSB references. The advantage of the present scheme is its simplicity. The extra circuitry is needed is minimal and the control timing is relatively simple. However, the most vulnerable aspect of this design is the use of the coupling capacitors to produce the LSB reference. These capacitors must be exactly proportioned to the cell capacitance since any error in the ratio translates directly into a reduction in the noise margins.
Therefore, it is desirable to provide a scheme that provides the fast access advantage of the Furuyama implementation with the idea of local reference generation provided by Gillingham. Accordingly there is a need for a memory architecture which mitigates at least some of the above disadvantages.
In accordance with this invention there is provided a dynamic random access memory for storing one of N levels in each of a plurality of memory cells, the memory cells having storage capacitors coupled to bitline pairs through switches for writing and reading data to and from the memory cells, the memory comprising:
(a) at least Nxe2x88x921 bitline pairs, each bitline pair being divided into Nxe2x88x921 sub-bitlines by first switches therebetween; the sub-bitline pairs of each bitline being coupled to adjacent sub-bitline pairs by second switches therebetween, to form Nxe2x88x921 groups of sub-bitlines each for producing one of Nxe2x88x921 reference voltages;
(b) sense amplifiers coupled to each sub-bitline pair;
(c) Nxe2x88x921 sub-bitline pairs each having reference cells for selective coupling thereto;
(d) (Nxe2x88x922)(Nxe2x88x921) sub-bitline pairs each having generate cells for selective coupling thereto; and
(e) sub-bitline pairs being selectively connected in a group through switches such that:
the sub-bitlines in said group are precharged to one of a plurality of voltages;
one of said (Nxe2x88x921) reference voltages is generated by shorting together sub-bitlines in said group; and
the reference voltage is stored in a reference cell in one of said bit-line pairs in said group.